1. Field of the Invention
The present invention relates to the field of programmable logic devices and more specifically to a latch circuit having dual n-type transistor drivers.
2. Prior Art
The manufacture and use of programmable logic devices (PLDs) which includes a memory array for programming the PLD are well known in the prior art. In many instances, erasable programmable read-only memory (EPROM) arrays are used in the PLD. The memory array is programmable wherein the stored program in combination with the logic provided in the macrocells provide for customization of a PLD for a particular application. Various PLD architectures are known in the prior art. For example, two U.S. Pat. Nos. to Hartmann et al., 4,609,986 and 4,617,479, as well as a patent to Birkner et al., 4,124,899, disclose and teach examples of prior art programmable logic arrays. An application of a PLD is taught in Hallenbeck et al., 4,761,647.
Generally, memory arrays of a PLD are arranged into a row and column matrix wherein inputs are coupled to the various row lines and outputs from the memory are obtained from the column lines of the memory array. In the operation of a PLD, latches or latch/registers are needed for latching information to and from the PLD. For example, when input signals are to be coupled to the input of the memory array, latches are typically used to latch in the information. Furthermore, when information is coupled as an output, latches are also used to latch the output of the memory array to the macrocells. Therefore, although latches are not essential to the operation of a PLD, they are typically used to latch and store information.
When a complementary metal-oxide-semiconductors (CMOS) technology is used to design a given device, latches for the device are also designed using this CMOS technology. Designs utilizing CMOS technology use a pair of CMOS transistors to provide the basic driver function. That is, a typical CMOS driver is comprised of a p-type transistor and a n-type transistor coupled in series between Vcc and Vss, wherein the output of the driver is taken at the drain junction of the two transistors. The gates of the two transistors are coupled together, such that when driven, one or the other transistor conducts causing the output to latch to vcc or Vss. However, the standard CMOS driver exhibits certain properties which are disadvantageous when implemented in a CMOS PLD. The present invention provides an improved latch circuit for latching information in a CMOS device and particularly in a CMOS PLD.